1. Field of the Invention
The present invention generally relates to a method for fabricating a pixel structure, and more particularly, to a method for fabricating a semiconductor layer by a laser ablation process.
2. Description of Related Art
A display functions as an interface between man and machines in addition to displaying images, wherein a flat display plays a major role in development tendency of the display technology today. A flat display is mainly categorized into organic electroluminescence displays (OELDs), plasma displays, and thin film transistor liquid crystal displays (TFT LCDs), wherein the TFT LCD is counted as the most popular one. In general, a TFT LCD is mainly composed of a thin film transistor array substrate, a color filter substrate and a liquid crystal layer. The TFT array substrate includes a plurality of scan lines, a plurality of data lines and a plurality of pixel structures arranged in array, and each pixel structure is respectively electrically connected to a corresponding scan line and a corresponding data line.
FIGS. 1A-1G are diagrams showing a conventional method for fabricating a pixel structure. Referring to FIG. 1A, a substrate 10 is first provided and then a gate 20 is formed on the substrate 10 by using a first photolithography and etching process. Next, as shown in FIG. 1B, a gate dielectric layer 30 is formed on the substrate 10 to cover the gate 20. Next, as shown in FIG. 1C, a channel layer 40 is formed over the gate 20 and on the gate dielectric layer 30 by using a second photolithography and etching process. Next, as shown in FIG. 1D, a source 50 and a drain 60 are formed on a partial region of the channel layer 40 and a partial region of the gate dielectric layer 30 by using a third photolithography and etching process. Usually, the channel layer 40 is made of amorphous silicon (a-Si). In order to reduce the contact impedances between the channel layer 40 and the source 50, and between the channel layer 40 and the drain 60, an ion doping process is conducted on the a-Si surface to form an N-type doping region.
Next, as shown in FIG. 1D, the source 50 and the drain 60 are respectively extended from both sides of the channel layer 40 onto the gate dielectric layer 30 and expose a partial region of the channel layer 40. Next, as shown in FIG. 1E, a passivation layer 70 is formed on the substrate 10 to cover the gate dielectric layer 30, the channel layer 40, the source 50 and the drain 60. Next, as shown in FIG. 1F, a fourth photolithography and etching process is used to pattern the passivation layer 70 so as to form a via hole H in the passivation layer 70. As shown in FIG. 1F, the via hole H in the passivation layer 70 exposes a portion of the drain 60. Moreover, as shown in FIG. 1G, a fifth photolithography and etching process is used to form a pixel electrode 80 on the passivation layer 70. As shown in FIG. 1G, the pixel electrode 80 can be electrically connected to the drain 60 through the via hole H. The fabrication of a pixel structure 90 is accomplished when the pixel electrode 80 has been formed.
As described above, a conventional pixel structure 90 is fabricated mainly by using five photolithography and etching processes. In other words, five photolithography and etching processes with different patterns are required for fabricating the pixel structure 90. Since the cost of each photo-mask used in the photolithography and etching process is quite high and therefore the fabrication cost can be significantly reduced by decreasing the number of the photolithography and etching processes.
In addition, along with increasing size of a TFT LCD panel, the photo-mask size for fabricating the TFT LCD panel is accordingly larger. A photo-mask with large dimension would be even higher, thus, the fabrication cost of the pixel structure 90 cannot be reduced.